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fir_filter
- 使用Verilog编程实现的分布式FIR滤波器源码，经过调试能够完成功能-Distributed programming using the Verilog source code FIR filters, after a debugging feature to complete
a
- 个人整理的关于FIR滤波器、加法器、减法器的verilog程序，供大家下载-It’s about some programs about filter，and some others I‘ll be happy if it s better for you~~~
firVerilog
- 用verilog语言编写的一个FIR滤波器的程序-Verilog language with a FIR filter process
firfilter14
- 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
fir_srg
- 该程序是利用Verlag HDL硬件描述语言实现的fir数字滤波器，希望对刚学习verilog的朋友有所帮助。-The procedure is to use Verlag HDL hardware descr iption language implementation of fir digital filters, just want to help a friend learn verilog.
ser_fir
- 用verilog实现一个8阶的改进串行FIR低通滤波器，输入数据位宽为12比特,经符号扩展后变为13比特。-With verilog order to achieve an improvement of 8 serial FIR low-pass filter, the input data bit width of 12 bits by sign extension into a 13-bit after.
fir_16
- 用Verilog写的fir滤波器，16阶8位位宽，看看吧-Written using Verilog fir filter, 16-order 8-bit wide, to see if it
FIR_chanbing
- 串并结构的FIR滤波器,Verilog语言编写，希望对大家有帮助-String and the structure of FIR filter, Verilog language, we want to help
fir_filter
- 一种fir滤波器的verilog程序，非常实用-fir filter very good write by verilog
LPF
- 数字低通FIR滤波器Verilog实现代码-Verilog digital FIR filter implementation code
firlms
- 基于FPGA的自适应FIR滤波器的verilog设计与实现-Adaptive FIR Filter Based FPGA Design and Implementation of verilog
robust_fir_latest.tar
- RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh scr ipt in the run directory (notice that the run scr ipts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 differe
fir_filter_generator
- FIR有限冲击响应滤波器verilog代码和测试-FIR finite FIR filter verilog code and test
8_oeder_signed_parellel_DA_FIR
- 本程序使用Verilog编写的程序。 本例是1个8阶对称系数的FIR滤波器，采用并行分布式算法。输入位宽为12位，输入是有符号的，即有正有负。-it s a program with Verilog
firfilt
- FIR滤波器verilog源代码，经过fpga验证可以被综合。-FIR filter verilog source code, fpga verification can be integrated.
filter_dds_10.29_7.2
- 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
TverilogFIRh
- 基于verilog的FIR滤波器程序设计（调试过的的）-verilog ， -Verilog program of FIR filter design (debug)-Verilog,
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
rc_flt
- 基于FPGA实现的64阶升余弦FIR并行滤波器，采用iso18000.6c标准实现，具有很好的低通滤波效果，已通过后仿上板验证，采用verilog语言实现。-64 order raised cosine FIR FPGA-based parallel filters, implemented using iso18000.6c standard with a low-pass filtering effect imitation on the board has passed validatio
FIR_lowpass
- FIR 滤波器 verilog 语言编写 很实用-FIR filter design